SMMU_CB10_TTBR0_high (SMMU500) Register Description
| Register Name | SMMU_CB10_TTBR0_high |
|---|---|
| Offset Address | 0x000001A024 |
| Absolute Address | 0x00FD81A024 (SMMU_GPV) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | The Translation Table Base register 0 holds the base address of the translation table 0. |
SMMU_CB10_TTBR0_high (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| ASID | 31:16 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
| address | 15:0 | rwNormal read/write | 0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |