SMMU_CB7_TCR_lpae (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID: UG1087
Release Date: 2024-03-13
Revision: 1.10

SMMU_CB7_TCR_lpae (SMMU500) Register Description

Register Name	SMMU_CB7_TCR_lpae
Offset Address	0x0000017030
Absolute Address	0x00FD817030 (SMMU_GPV)
Width	32
Type	rwNormal read/write
Reset Value	0x00000000
Description	The Translation Table base control register determines which of the TTBRs(SMMU_CBn_TTBR0 or SMMU_CBn_TTBR1) defines the base address for the translation table walk that is required when the input address is not found in the TLB.

SMMU_CB7_TCR_lpae (SMMU500) Register Bit-Field Summary

Field Name	Bits	Type	Reset Value	Description
EAE	31	rwNormal read/write	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSCFG1_TG1	30	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SH1	29:28	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ORGN1	27:26	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IRGN1	25:24	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
EPD1	23	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
A1	22	rwNormal read/write	0x0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
T1SZ_5_3	21:19	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
T1SZ_2_0_PASIZE	18:16	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
NSCFG0_TG0	14	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SH0	13:12	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
ORGN0	11:10	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
IRGN0	9:8	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SL0_1_EPD0	7	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
SL0_0	6	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
PD1_T0SZ_5	5	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
S_PD0_T0SZ_4	4	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
T0SZ_3_0	3:0	rwNormal read/write	0	Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details