DMA_buffer_boundary_register (NAND) Register Description
| Register Name | DMA_buffer_boundary_register |
|---|---|
| Offset Address | 0x0000000054 |
| Absolute Address | 0x00FF100054 (NAND) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | DMA Buffer Boundary. |
Applies only to MDMA transaction mode.
DMA_buffer_boundary_register (NAND) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:4 | razRead as zero | 0x0 | reserved |
| dma_bound_int_en | 3 | rwNormal read/write | 0x0 | DMA Buffer Boundary Interrupt enable: 0: disable, masked. 1: enable. Note: Change this value only when controller is not communicating with the memory device. |
| DMA_buffer_boundary_register | 2:0 | rwNormal read/write | 0x0 | To perform long DMA transfer, the System Address register is updated at every system boundary during the DMA transfer. Program the size of the contiguous buffer in the system memory. The DMA transfer waits at every boundary specified by this bit field and generates the DMA Interrupt to request the driver to update the System Address register for the next buffer transfer. Buffer size: 000: 4 KB 001: 8 KB 010: 16 KB 011: 32 KB 100: 64 KB 101: 128 KB 110: 256 KB 111: 512 KB Note: Change this value only when controller is not communicating with the memory device. |