Channel_sts (UART) Register Description
| Register Name | Channel_sts |
|---|---|
| Offset Address | 0x000000002C |
| Absolute Address |
0x00FF00002C (UART0) 0x00FF01002C (UART1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Channel Status Register |
The read only Channel Status register is provided to enable the continuous monitoring of the raw unmasked status information of the UART design. Bits [4:0] and [14:10] are not latched and provide raw status of the FIFO flags, such that if the FIFO level changes these bits are updated immediately.
Channel_sts (UART) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:15 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| TNFUL | 14 | roRead-only | 0x0 | Transmitter FIFO Nearly Full continuous status: This indicates that there is not enough space for the number of bytes currently specified in the WSIZE bits in the Mode register. If a write were currently attempted it would cause an overflow. Note that when WSIZE is 00, this assumes that a two byte write would be attempted and hence a single byte write is still possible without overflow by driving byte_sel low for the write. 0: More than one byte is unused in the Tx FIFO 1: Only one byte is free in the Tx FIFO |
| TTRIG | 13 | roRead-only | 0x0 | Transmitter FIFO Trigger continuous status: 0: Tx FIFO fill level is less than TTRIG 1: Tx FIFO fill level is greater than or equal to TTRIG. |
| FDELT | 12 | roRead-only | 0x0 | Receiver flow delay trigger continuous status: 0: Rx FIFO fill level is less than FDEL 1: Rx FIFO fill level is greater than or equal to FDEL |
| TACTIVE | 11 | roRead-only | 0x0 | Transmitter state machine active status: 0: inactive state 1: active state |
| RACTIVE | 10 | roRead-only | 0x0 | Receiver state machine active status: 0: inactive state 1: active state |
| Reserved | 9:5 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| TFUL | 4 | roRead-only | 0x0 | Transmitter FIFO Full continuous status: 0: Tx FIFO is not full 1: Tx FIFO is full |
| TEMPTY | 3 | roRead-only | 0x0 | Transmitter FIFO Empty continuous status: 0: Tx FIFO is not empty 1: Tx FIFO is empty |
| RFUL | 2 | roRead-only | 0x0 | Receiver FIFO Full continuous status: 1: Rx FIFO is full 0: Rx FIFO is not full |
| REMPTY | 1 | roRead-only | 0x0 | Receiver FIFO Full continuous status: 0: Rx FIFO is not empty 1: Rx FIFO is empty |
| RTRIG | 0 | roRead-only | 0x0 | Receiver FIFO Trigger continuous status: 0: Rx FIFO fill level is less than RTRIG 1: Rx FIFO fill level is greater than or equal to RTRIG |