ATTR_53 (PCIE_ATTRIB) Register Description
| Register Name | ATTR_53 |
|---|---|
| Offset Address | 0x00000000D4 |
| Absolute Address | 0x00FD4800D4 (PCIE_ATTRIB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00003D48 |
| Description | ATTR_53 |
This register should only be written to during reset of the PCIe block
ATTR_53 (PCIE_ATTRIB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr_pm_cap_rsvd_04 | 15 | rwNormal read/write | 0x0 | Reserved bit 20 of the PM Capabilities Register. This is expected to be tied to 0. |
| attr_pm_cap_pmesupport | 14:10 | rwNormal read/write | 0xF | PME Support. These five bits indicate support for D3cold, D3hot, D2, D1 and D0 respectively. Transferred to the PM Capabilities register[31:27]. |
| attr_pm_cap_pme_clock | 9 | rwNormal read/write | 0x0 | When set indicates that a PCI clock is required for PME generation. This must be set to 0, [per the specification. The value is transferred to the PM Capabilities Register[19]. |
| attr_pm_cap_on | 8 | rwNormal read/write | 0x1 | Indicates that the PM structures exists. If this is FALSE, then the PM structure cannot be accessed via either the link or the management port. |
| attr_pm_cap_nextptr | 7:0 | rwNormal read/write | 0x48 | PM Capabilitys Next Capability Offset pointer to the next item in the capabilities list, or 00h if this is the final capability. |