AXI_RBL1 (VCU_DEC_TOP) Register Description
| Register Name | AXI_RBL1 |
|---|---|
| Offset Address | 0x0000009224 |
| Absolute Address | 0x00A0029224 (VCU_DECODE) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | AXI Read Bandwidth Limiter 1 |
AXI_RBL1 (VCU_DEC_TOP) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| AxiReadBwLimThr1 | 31:16 | rwNormal read/write | 0x0 | Port 1 Read Bandwidth Limiter Threshold: threshold, in units of 128-bit words, for the number of read accesses that can be requested on the AXI master port 1 during the read bandwidth limiter time window. As soon as the threshold is exceeded at the end of an AXI burst, read requests are stalled until the end of the time window. |
| AxiReadBwLimWin1 | 15:0 | rwNormal read/write | 0x0 | Port 1 Read Bandwidth Limiter Window: this field configures the time window, in units of aclk clock cycles, of the read bandwidth limiter for the 128-bit AXI master port 1. A zero value disables the bandwidth limiter. |