PP4C (SATA_AHCI_VENDOR) Register Description
| Register Name | PP4C |
|---|---|
| Offset Address | 0x0000000014 |
| Absolute Address | 0x00FD0C00B4 (SATA_AHCI_VENDOR) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x064A0813 |
| Description | Port Phy Configuration 4. |
Controls the configuration of the Phy Control Burst timing for the COM parameters for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
PP4C (SATA_AHCI_VENDOR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PTST | 31:24 | rwNormal read/write | 0x6 | PTST: Partial to Slumber timer value, specific delay the controller should apply while in partial before entering slumber. The value is bases on the system clock divided by 128, total delay = (Sys Clock Period) * PTST * 128 |
| SFD | 23:16 | rwNormal read/write | 0x4A | SFD: Signal Failure Detection, if the signal detection de-asserts for a time greater than this then the OOB detector will determine this is a line idle and cause the PhyInit state machine to exit the Phy Ready State. A value of zero disables the Signal Failure Detector. The value is based on the OOB Detector Clock typically (PMCLK Clock Period) * SFD giving a nominal time of 500ns based on a 150MHz PMCLK. |
| BNM | 15:8 | rwNormal read/write | 0x8 | BNM: COM Burst Nominal. |
| BMX | 7:0 | rwNormal read/write | 0x13 | BMX: COM Burst Maximum. |