INT_ANY_0 (GPIO) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

INT_ANY_0 (GPIO) Register Description

Register NameINT_ANY_0
Offset Address0x0000000224
Absolute Address 0x00FF0A0224 (GPIO)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Any Edge Sensitive (GPIO Bank0, MIO)

If INT_TYPE is set to edge sensitive, then this register enables an interrupt event on both rising and falling edges. This register is ignored if INT_TYPE is set to level sensitive. This register controls bank0, which corresponds to MIO[25:0].

INT_ANY_0 (GPIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:26razRead as zero0x0Not used, read back as zero
INT_ON_ANY_025:0rwNormal read/write0x0Interrupt edge triggering mode
0: trigger on single edge, using configured interrupt polarity
1: trigger on both edges
Each bit configures the corresponding pin within the 26-bit bank