| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:11 | razRead as zero | 0x0 | Status for an address decode error interrupt. |
| UE_RMW | 10 | wtcReadable, write a 1 to clear | 0x0 | Uncorrectable error occurd during executing sub width write transaction |
| FIX_BURST_WR | 9 | wtcReadable, write a 1 to clear | 0x0 | FIX Burst Detected on AXI write channel |
| FIX_BURST_RD | 8 | wtcReadable, write a 1 to clear | 0x0 | FIX Burst Detected on AXI read channel |
| ECC_UE | 7 | wtcReadable, write a 1 to clear | 0x0 | Uncorrecteble ECC ERROR detected, refer UE_FE registers for more information |
| ECC_CE | 6 | wtcReadable, write a 1 to clear | 0x0 | Correcteble ECC ERROR detected, refer CE_FE registers for more information |
| LOCK_ERR_WR | 5 | wtcReadable, write a 1 to clear | 0x0 | LOCK access on write channle (OCM does not support AXI LOCK transaction) |
| LOCK_ERR_RD | 4 | wtcReadable, write a 1 to clear | 0x0 | LOCK access on read channle (OCM does not support AXI LOCK transaction) |
| INV_OCM_WR | 3 | wtcReadable, write a 1 to clear | 0x0 | Poison assetion on write channel |
| INV_OCM_RD | 2 | wtcReadable, write a 1 to clear | 0x0 | Poison assetion on read channel |
| PWR_DWN | 1 | wtcReadable, write a 1 to clear | 0x0 | sofware access topower down bank |
| INV_APB | 0 | wtcReadable, write a 1 to clear | 0x0 | APB (register) access occurs to an unimplemented space |