ERR_STATUS2 (XPPU) Register Description
| Register Name | ERR_STATUS2 |
|---|---|
| Offset Address | 0x0000000008 |
| Absolute Address | 0x00FF980008 (LPD_XPPU) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Error Status, Reg 2. Poisoned Master ID. |
The first violation is recorded. Once an ISR[7:1] status bit is set, subsequent violations are not recorded, but their transactions are poisoned. The status bits are cleared by a system reset and can be cleared by software.
ERR_STATUS2 (XPPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:10 | roRead-only | 0x0 | reserved |
| AXI_ID | 9:0 | roRead-only | 0x0 | Master ID from a poisoned read or write transaction. Read-only. |