AUX_PWR_STATE (PMU_GLOBAL) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

AUX_PWR_STATE (PMU_GLOBAL) Register Description

Register NameAUX_PWR_STATE
Offset Address0x0000000104
Absolute Address 0x00FFD80104 (PMU_GLOBAL)
Width32
TyperoRead-only
Reset Value0x000FF080
DescriptionMemory Retention and RPU Emulation State.

Applies to RAM memory retention: 0: active state. 1: low-power, inaccessible in retention state. Applies to RPU and APU Emulation state: 0: normal RPU/APU state. 1: low-power, RPU/APU emulation state. There are 5 power islands: RPUs, APU[0:3}. Emulation mode is used for debug, because it does not actually power down the CPU. The island is logically off, but the power supply is still on so debug accesses via DAP can peek and poke the system. All bits are read-only. Register is reset only by a POR reset.

AUX_PWR_STATE (PMU_GLOBAL) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
ACPU3_Emulation31roRead-only0x0APU core 3 emulation state.
ACPU2_Emulation30roRead-only0x0APU core 2 emulation state.
ACPU1_Emulation29roRead-only0x0APU core 1 emulation state.
ACPU0_Emulation28roRead-only0x0APU core 0 emulation state.
RPU_Emulation27roRead-only0x0RPU MPCore emulation state.
Reserved26:20roRead-only0x0reserved
OCM_Bank319roRead-only0x1OCM Bank 3 retention state.
OCM_Bank218roRead-only0x1OCM Bank 2 retention state.
OCM_Bank117roRead-only0x1OCM Bank 1 retention state.
OCM_Bank016roRead-only0x1OCM Bank 0 retention state.
TCM1B15roRead-only0x1RPU core 1, TCM_B retention state.
TCM1A14roRead-only0x1RPU core 1, TCM_A retention state.
TCM0B13roRead-only0x1RPU core 0, TCM_B retention state.
TCM0A12roRead-only0x1RPU core 0, TCM_A retention state.
Reserved11:9roRead-only0x0reserved
Reserved 8roRead-only0x0reserved
L2_Bank0 7roRead-only0x1APU L2 Cache RAM retention state.
Reserved 6:0roRead-only0x0reserved