SMMU_CB2_TLBSTATUS (SMMU500) Register Description
| Register Name | SMMU_CB2_TLBSTATUS |
|---|---|
| Offset Address | 0x00000127F4 |
| Absolute Address | 0x00FD8127F4 (SMMU_GPV) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Indicates the status of any TLB maintenance operations issued before the most recent SMMU_CBn_TLBSYNC operation |
SMMU_CB2_TLBSTATUS (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| SACTIVE | 0 | roRead-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |