APM0_RESULT8 (VCU_SLCR) Register Description
| Register Name | APM0_RESULT8 |
|---|---|
| Offset Address | 0x000000012C |
| Absolute Address | 0x00A004012C (VCU_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | APM0_RESULT8 |
APM0_RESULT8 (VCU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| validity_check | 31 | roRead-only | 0x0 | This signal will toggle in alternate timing window. This is required for safe reading of accumulated read and write latencies parameters which requires more then one APM access. This bit field is read with all the latency related APB registers and this is expected to be same for all those registers. |
| Reserved | 30:28 | razRead as zero | 0x0 | reserved |
| accum_rd_lat0 | 27:0 | roRead-only | 0x0 | 28 LSBs of accumulated read latency for 1st FIFO over configured timing window. |