reg_presentstate (SDIO) Register Description
| Register Name | reg_presentstate |
|---|---|
| Offset Address | 0x0000000024 |
| Absolute Address |
0x00FF160024 (SD0) 0x00FF170024 (SD1) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00080000 |
| Description | SDIO Controller Status, read-only. |
reg_presentstate (SDIO) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| sdif_dat7in_dsync | 28 | roRead-only | 0x0 | This status is used to check DAT line level to recover from errors, and for debugging. |
| sdif_dat6in_dsync | 27 | roRead-only | 0x0 | This status is used to check DAT line level to recover from errors, and for debugging. |
| sdif_dat5in_dsync | 26 | roRead-only | 0x0 | This status is used to check DAT line level to recover from errors, and for debugging. |
| sdif_dat4in_dsync | 25 | roRead-only | 0x0 | This status is used to check DAT line level to recover from errors, and for debugging. |
| sdif_cmdin_dsync | 24 | roRead-only | 0x0 | This status is used to check DAT line level to recover from errors, and for debugging. |
| sdif_dat3in_dsync | 23 | roRead-only | 0x0 | This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. |
| sdif_dat2in_dsync | 22 | roRead-only | 0x0 | This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. |
| sdif_dat1in_dsync | 21 | roRead-only | 0x0 | This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. |
| sdif_dat0in_dsync | 20 | roRead-only | 0x0 | This status is used to check DAT line level to recover from errors, and for debugging. This is especially useful in detecting the busy signal level from DAT[0]. |
| sdif_wp_dsync | 19 | roRead-only | 0x1 | The Write Protect Switch is supported for memory and combo cards.This bit reflects the inversion of the SDx_WP pin. 0: Write protected, SDx_WP pin = High. 1: Write enabled, SDx_WP pin = Low. |
| sdif_cd_n_dsync | 18 | roRead-only | 0x0 | This bit reflects the inverse value of the SDCD# pin. 0: No Card present, SDx_CDn pin = High. 1: Card present, SDx_CDn pin = Low. |
| sdhccarddet_statestable_dsync | 17 | roRead-only | 0x0 | This bit is used for testing. If it is 0, the Card Detect Pin Level is not stable. If this bit is set to 1,it means the Card Detect Pin Level is stable. The Software Reset For All in the Software Reset Register shall not affect this bit. 0 Reset of Debouncing 1 No Card or Inserted |
| sdhccarddet_inserted_dsync | 16 | roRead-only | 0x0 | Card insertion status flag. Read-only. Changing from 0 to 1 generates a Card Insertion interrupt in the Normal Interrupt Status register. Changing from 1 to 0 generates a Card Removal interrupt in the Normal Interrupt Status register. The Software Reset For All in the Software Reset register does not affect this bit. If a Card is removed while its power is on and its clock is oscillating, the controller clears SD Bus Power in the Power Control register and SD Clock Enable in the Clock control register. In addition the Host Driver should clear the controller using the Software Reset For All in Software register. The card detect is active regardless of the SD Bus Power. 0: Reset or Debouncing or No Card. 1: Card Inserted. |
| sdhcdmactrl_piobufrdena | 11 | roRead-only | 0x0 | This status is used for non-DMA read transfers.This read only flag indicates that valid data exists in the host side buffer status. If this bit is 1, readable data exists in the buffer. A change of this bit from 1 to 0 occurs when all the block data is read from the buffer. A change of this bit from 0 to 1 occurs when all the block data is ready in the buffer and generates the Buffer Read Ready Interrupt. 0 Read Disable 1 Read Enable |
| sdhcdmactrl_piobufwrena | 10 | roRead-only | 0x0 | This status flag is used with write transfers via register writes (not DMA). Read-only. This flag indicates if space is available for writing data. 0: do not write to the register port. 1: data can be written to the buffer via the register port. A change from 1 to 0 indicates the buffer is full. A change from 0 to 1 occurs when top of block data can be written to the buffer and generates the Buffer Write Ready Interrupt. |
| sdhcdmactrl_rdxferactive | 9 | roRead-only | 0x0 | Completion of a read transfer flag. Read-only. This bit is set to 1 for either of the following conditions: * After the end bit of the read command, or * When writing a 1 to continue Request in the Block Gap Control register to restart a read transfer. This bit is cleared to 0 for either of the following conditions: * When the last data block as specified by block length is transferred to the system, or * When all valid data blocks have been transferred to the system and no current block transfers are being sent as a result of the Stop At Block Gap Request set to 1. A transfer complete interrupt is generated when this bit changes to 0. 0: No valid data 1: Transferring data |
| sdhcdmactrl_wrxferactive | 8 | roRead-only | 0x0 | This status indicates a write transfer is active. If this bit is 0, it means no valid write data exists in the HC. This bit is set in either of the following cases: * After the end bit of the write command. * When writing a 1 to Continue Request in the Block Gap Control register to restart a write transfer. This bit is cleared in either of the following cases: * After getting the CRC status of the last data block as specified by the transfer count (Single or Multiple) * After getting a CRC status of any block where data transmission is about to be stopped by a Stop At Block Gap Request. During a write transaction, a Block Gap Event interrupt is generated when this bit is changed to 0, as a result of the Stop At Block Gap Request being set. This status is useful for the HD in determining when to issue commands during write busy. 0 No valid data 1 Transferring data |
| sdhcsdctrl_retuningreq_dsync | 3 | roRead-only | 0x0 | Controller may request that the Host Driver executes the re-tuning sequence using this bit. Re-tune the I/O timing when the data window is shifted by temperature changes or to improve timing margins to receive correct data. 0: Sampling clock is okay (its fixed timing or well tuned). 1: Re-tune the sampling clock. This bit is set = 0 when a command is issued by setting the Execute Tuning bit in the Host Control 2 register. When software writes this bit from a 0 to 1 and [Sampling Clock Select] = 1 (not fixed sampling), the controller triggers the re-tune event. Refer to Normal Interrupt registers for more detail. |
| sdhcdmactrl_datalineactive | 2 | roRead-only | 0x0 | SD_DAT signal I/O activity: 0: inactive. 1: active. |
| presentstate_inhibitdat | 1 | roRead-only | 0x0 | Dual purpose status indicator: * SD_DAT I/O is active, or * Read transfer Active is set to 1. [ ] 0: controller can issue the next SD command. Commands with busy signal belong to Command Inhibit (DAT) (ex. R1b, R5b type). When the status indicator changes from a 0 to 1, the Transfer Complete interrupt asserts. Note: The SD Host Driver can save registers in the range of 000-00Dh; for a suspend transaction this bit changes from 1 to 0. 0 Can issue command which uses the DAT line 1 Cannot issue command which uses the DATline |
| presentstate_inhibitcmd | 0 | roRead-only | 0x0 | Controller State. 0: The CMD line is not in use and the controller can issue a SD command using the CMD line. This bit is set immediately after the Command register (00Fh) is written. This bit is cleared when the command response is received. Even if the Command Inhibit (DAT) is set to 1, Commands using only the CMD line can be issued if this bit is 0. Changing from 1 to 0 generates a Command complete interrupt in the Normal Interrupt Status register. If the controller cannot issue the command because of a command conflict error or because of Command Not Issued By Auto CMD12 Error, this bit remains a 1 and the Command Complete interrupt is not set. Status issuing Auto CMD12 is not read from this bit. Auto CMD12 and Auto CMD23 consist of two responses. In this case, this bit is not cleared by the response of CMD12 or CMD23 but cleared by the response of a read/write command. Status issuing Auto CMD12 is not read from this bit. So if a command is issued during Auto CMD12 operation, controller issues two commands: CMD12 and a command set by Command register. |