ITC_CPU_IRQ_MSK (VCU_DEC_TOP) Register Description
| Register Name | ITC_CPU_IRQ_MSK |
|---|---|
| Offset Address | 0x0000009104 |
| Absolute Address | 0x00A0029104 (VCU_DECODE) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | CPU Interrupt Mask |
ITC_CPU_IRQ_MSK (VCU_DEC_TOP) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:8 | rwNormal read/write | 0x0 | Reserved |
| Extirq1InterruptMask | 7 | rwNormal read/write | 0x0 | EXTIRQ1 interrupt mask: 0: disable EXTIRQ1 interrupt source 1: enable EXTIRQ1 interrupt source |
| Extirq0InterruptMask | 6 | rwNormal read/write | 0x0 | EXTIRQ0 interrupt mask: 0: disable EXTIRQ0 interrupt source 1: enable EXTIRQ0 interrupt source |
| Rresp1InterruptMask | 5 | rwNormal read/write | 0x0 | RRESP1 interrupt mask: 0: disable RRESP1 interrupt source 1: enable RRESP1 interrupt source |
| Bresp1InterruptMask | 4 | rwNormal read/write | 0x0 | BRESP1 interrupt mask: 0: disable BRESP1 interrupt source 1: enable BRESP1 interrupt source |
| Rresp0InterruptMask | 3 | rwNormal read/write | 0x0 | RRESP0 interrupt mask: 0: disable RRESP0 interrupt source 1: enable RRESP0 interrupt source |
| Bresp0InterruptMask | 2 | rwNormal read/write | 0x0 | BRESP0 interrupt mask: 0: disable BRESP0 interrupt source 1: enable BRESP0 interrupt source |
| Reserved | 1 | rwNormal read/write | 0x0 | Reserved |
| McuToCpuInterruptMask | 0 | rwNormal read/write | 0x0 | MCU-to-CPU interrupt mask: 0: disable MCU-to-CPU interrupt source 1: enable MCU-to-CPU interrupt source |