PIT2_PRELOAD (PMU_IOMODULE) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

PIT2_PRELOAD (PMU_IOMODULE) Register Description

Register NamePIT2_PRELOAD
Offset Address0x0000000060
Absolute Address 0x00FFD40060 (PMU_IOMODULE)
Width32
TyperoRead-only
Reset Value0x00000000
DescriptionPIT2 Preload Register

The value written to this register determines the period between two consecutive PIT2_Interrupt events. The period is the value written to the register + 2 count events.

PIT2_PRELOAD (PMU_IOMODULE) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
PIT2_PRELOAD31:0roRead-only0x0Register holds the timer period