L3_TM_DIG_21 (SERDES) Register Description
| Register Name | L3_TM_DIG_21 |
|---|---|
| Offset Address | 0x000000D0A8 |
| Absolute Address | 0x00FD40D0A8 (SERDES) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Register value is generated by Vivado PCW. |
L3_TM_DIG_21 (SERDES) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TM_DIG_21_31_8_rsvd | 31:8 | roRead-only | 0x0 | Value generated by PCW. |
| Reserved | 7:5 | roRead-only | 0x0 | Value generated by PCW. |
| comma_location_rst | 4 | rwNormal read/write | 0x0 | Value generated by PCW. |
| ssc_wait_cnt | 3:2 | rwNormal read/write | 0x0 | Value generated by PCW. |
| comma_pre_lock_thresh | 1:0 | rwNormal read/write | 0x0 | Value generated by PCW. |