INIT1 (DDRC) Register Description
| Register Name | INIT1 |
|---|---|
| Offset Address | 0x00000000D4 |
| Absolute Address | 0x00FD0700D4 (DDRC) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | SDRAM Initialization Register 1 |
This register is static. Static registers can only be written when the controller is in reset.
INIT1 (DDRC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| dram_rstn_x1024 | 24:16 | rwNormal read/write | 0x0 | DDR3/DDR4/LPDDR4: Number of cycles to assert SDRAM reset signal during init sequence. This should be set to a minimum of 1 |
| final_wait_x32 | 14:8 | rwNormal read/write | 0x0 | Cycles to wait after completing the SDRAM initialization sequence before starting the dynamic scheduler. Unit: Counts of a global timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero. |
| pre_ocd_x32 | 3:0 | rwNormal read/write | 0x0 | Wait period before driving the OCD complete command to SDRAM. Unit: Counts of a global timer that pulses every 32 clock cycles. There is no known specific requirement for this; it may be set to zero. |