Intrpt_Enable (I2C) Register Description
| Register Name | Intrpt_Enable |
|---|---|
| Offset Address | 0x0000000024 |
| Absolute Address |
0x00FF020024 (I2C0) 0x00FF030024 (I2C1) |
| Width | 16 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Interrupt Enable Register |
This register has the same format as the interrupt status register. Setting a bit in the interrupt enable register clears the corresponding mask bit in the interrupt mask register, effectively enabling corresponding interrupt to be generated.
Intrpt_Enable (I2C) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 15:10 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| ARB_LOST | 9 | woWrite-only | 0x0 | arbitration lost 1 = enable this interrupt |
| Reserved | 8 | roRead-only | 0x0 | Reserved, read as zero, ignored on write. |
| RX_UNF | 7 | woWrite-only | 0x0 | FIFO receive underflow 1 = enable this interrupt |
| TX_OVF | 6 | woWrite-only | 0x0 | FIFO transmit overflow 1 = enable this interrupt |
| RX_OVF | 5 | woWrite-only | 0x0 | Receive overflow 1 = enable this interrupt |
| SLV_RDY | 4 | woWrite-only | 0x0 | Monitored slave ready 1 = enable this interrupt |
| TO | 3 | woWrite-only | 0x0 | Transfer time out 1 = enable this interrupt |
| NACK | 2 | woWrite-only | 0x0 | Transfer not acknowledged 1 = enable this interrupt |
| DATA | 1 | woWrite-only | 0x0 | More data 1 = enable this interrupt |
| COMP | 0 | woWrite-only | 0x0 | Transfer complete Will be set when transfer is complete 1 = enable this interrupt |