ATTR_4 (PCIE_ATTRIB) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

ATTR_4 (PCIE_ATTRIB) Register Description

Register NameATTR_4
Offset Address0x0000000010
Absolute Address 0x00FD480010 (PCIE_ATTRIB)
Width32
TyperwNormal read/write
Reset Value0x00001000
DescriptionATTR_4

This register should only be written to during reset of the PCIe block

ATTR_4 (PCIE_ATTRIB) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
attr_aer_cap_on12rwNormal read/write0x1Indicates that the AER structures exists. If this is FALSE, then the AER structure cannot be accessed via either the link or the management port, and AER will be considered to not be present for error management tasks (such as what types of error messages are sent if an error is detected).
attr_aer_cap_nextptr11:0rwNormal read/write0x0AERs Next Capability Offset pointer to the next item in the capabilities list, or 000h if this is the final capability.