SMMU_PIDR0 (SMMU500) Register Description
| Register Name | SMMU_PIDR0 |
|---|---|
| Offset Address | 0x0000000FE0 |
| Absolute Address | 0x00FD800FE0 (SMMU_GPV) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000081 |
| Description | Peripheral Identificaation register 0 |
SMMU_PIDR0 (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PartNumber0 | 7:0 | roRead-only | 0x81 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |