GICP1_IRQ_MASK (LPD_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

GICP1_IRQ_MASK (LPD_SLCR) Register Description

Register NameGICP1_IRQ_MASK
Offset Address0x0000008018
Absolute Address 0x00FF418018 (LPD_SLCR)
Width32
TyperoRead-only
Reset Value0xFFFFFFFF
DescriptionInterrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER.

GICP1_IRQ_MASK (LPD_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
src3131roRead-only0x1Gigabit Ethernet3 interrupt
src3030roRead-only0x1Gigabit Ethernet2 wakeup interrupt
src2929roRead-only0x1Gigabit Ethernet2 interrupt
src2828roRead-only0x1Gigabit Ethernet1 wakeup interrupt
src2727roRead-only0x1Gigabit Ethernet1 interrupt
src2626roRead-only0x1Ethernet0 wakeup interrupt
src2525roRead-only0x1Ethernet0 interrupt
src2424roRead-only0x1AMS interrupt
src2323roRead-only0x1AIB AXI interrupt
src2222roRead-only0x1ATB interrupt
src2121roRead-only0x1WDT in the CSUPMU: This is Edge trigger interrupt and Interrupt pulse width case be prograbble window from 40ns to 320ns. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for.
src2020roRead-only0x1WDT in the LPD (IOU). This is Edge trigger interrupt and Interrupt pulse width case be prograbble window from 40ns to 320ns. This signal synchronized using double-flops; due to this method of synchronization, the duration of the narrowest 'pulse' must be accounted for.
src1919roRead-only0x1SDIO1 wake interrupt
src1818roRead-only0x1SDIO0 wake interrupt
src1717roRead-only0x1SDIO1 interrupt
src1616roRead-only0x1SDIO0 interrupt
src1515roRead-only0x1Triple Time Counter3
src1414roRead-only0x1Triple Time Counter3
src1313roRead-only0x1Triple Time Counter3
src1212roRead-only0x1Triple Timer Counter2
src1111roRead-only0x1Triple Timer Counter2
src1010roRead-only0x1Triple Timer Counter2
src9 9roRead-only0x1Triple Timer counter1
src8 8roRead-only0x1Triple Timer counter1
src7 7roRead-only0x1Triple Timer counter1
src6 6roRead-only0x1Triple Timer counter0
src5 5roRead-only0x1Triple Timer counter0
src4 4roRead-only0x1Triple Timer counter0
src3 3roRead-only0x1APU_IPI0: OR of all of IPIs targeted to APU CPU
src2 2roRead-only0x1RPU_IPI1: OR of all of IPIs targeted to RPU CPU1
src1 1roRead-only0x1RPU_IPI0: OR of all of IPIs targeted to RPU CPU0
src0 0roRead-only0x1PL_IPI3: OR of all of IPIs targeted to RPU PL3