L2_PWR_CNTRL (PMU_LOCAL) Register Description
| Register Name | L2_PWR_CNTRL |
|---|
| Offset Address | 0x00000000B0 |
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| Absolute Address |
0x00FFD600B0 (PMU_LOCAL)
|
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| Width | 32 |
|---|
| Type | mixedMixed types. See bit-field details. |
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| Reset Value | 0x00000001 |
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| Description | L2 Cache Power Control. Reset by POR only. |
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Controls the on-chip power switch: 0: power off. 1: power on. Field can only be read or written by the PMU processor. This register maintains its contents during a System Reset.
L2_PWR_CNTRL (PMU_LOCAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:1 | roRead-only | 0x0 | reserved |
| Bank0 | 0 | rwNormal read/write | 0x1 | Power switch enable for the L2 cache. |