Interrupt_Register_1 (TTC) Register Description
| Register Name | Interrupt_Register_1 |
|---|---|
| Offset Address | 0x0000000054 |
| Absolute Address |
0x00FF110054 (TTC0) 0x00FF120054 (TTC1) 0x00FF130054 (TTC2) 0x00FF140054 (TTC3) |
| Width | 6 |
| Type | clronrdReadable, clears value on read |
| Reset Value | 0x00000000 |
| Description | Counter 1 Interval, Match, Overflow and Event interrupts |
Interrupt_Register_1 (TTC) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Ev | 5 | clronrdReadable, clears value on read | 0x0 | Event timer overflow interrupt |
| Ov | 4 | clronrdReadable, clears value on read | 0x0 | Counter overflow |
| M3 | 3 | clronrdReadable, clears value on read | 0x0 | Match 3 interrupt |
| M2 | 2 | clronrdReadable, clears value on read | 0x0 | Match 2 interrupt |
| M1 | 1 | clronrdReadable, clears value on read | 0x0 | Match 1 interrupt |
| Iv | 0 | clronrdReadable, clears value on read | 0x0 | Interval interrupt |