ATTR_17 (PCIE_ATTRIB) Register Description
| Register Name | ATTR_17 |
|---|---|
| Offset Address | 0x0000000044 |
| Absolute Address | 0x00FD480044 (PCIE_ATTRIB) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x0000FFFF |
| Description | ATTR_17 |
This register should only be written to during reset of the PCIe block
ATTR_17 (PCIE_ATTRIB) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| attr_bar5 | 15:0 | rwNormal read/write | 0xFFFF | For an endpoint, specifies mask/settings for Base Address Register (BAR) 5 if BAR4 is a 32-bit BAR, or the upper bits of {BAR5,BAR4} if BAR4 is the lower part of a 64-bit BAR. If BAR is not to be implemented, set to 32h00000000. See BAR4 description if this functions as the upper bits of a 64-bit BAR. For a switch or root, this must be set to: 0000_0000 = Prefetchable Memory Limit/Base Registers not implemented FFF0_FFF0 = 32-bit Prefetchable Memory Limit/Base implemented FFF1_FFF1 = 64-bit Prefetchable Memory Limit/Base implemented For an endpoint, bits are defined as follows: Memory Space BAR (not upper bits of BAR4) [0] = Mem Space Indicator (set to 0) [2:1] = Type field (00 for 32-bit; BAR5 cannot be lower part of a 64-bit BAR) [3] = Prefetchable (0 or 1) [31:4] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=memory aperture size in bytes. IO Space BAR 0] = IO Space Indicator (set to 1) [1] = Reserved (set to 0) [31:2] = Mask for writable bits of BAR; set uppermost 31:n bits to 1, where 2^n=i/o aperture size in bytes. |