| Field Name | Bits | Type | Reset Value | Description |
|---|
| PMPRA | 31:27 | rwNormal read/write | 0x7 | Power Management Primitive Rate Acknowledge (PMPRA): This value determines the number of PMACK primitives sent when a power management state transition is requested by the host. |
| POE | 26 | rwNormal read/write | 0x0 | Primitive Override Enable (POE): When set, this bit enables the replacement of a single primitive, as specified by Override Primitive/CD, when the Link Layer state machine is in the Prim Override State. This bit has to be toggled from a 0 to a 1 to enable this feature. |
| PRT | 25:16 | rwNormal read/write | 0x0 | Phy Ready Timer (PRT): These 10 bits specify the timeout value of the PhyReady Timer. If EnPhyReadyTimeOut is set, the Link Layer will count down on every rising edge of txWordClk, as long as PhyReady is de-asserted. When the counter reaches zero, a PhyReset will be issued to the Phy to try and re-establish communications with the far-end. The timer is initially loaded with a value equal to the concatenation of { Phy Ready Timer, 9h000}. |
| AIR | 15:8 | rwNormal read/write | 0xFF | Align Insertion Rate (AIR): The Serial ATA specification requires that the Link Layer sends a pair of ALIGN primitives at least every 254 DWords of data. This is achieved by setting Align Insertion Rate to 11111111. However, for test purposes it is possible to send ALIGNs at a higher rate. This can be achieved by setting Align Insertion Rate to a lower value i.e. (Align Insertion Rate-1) DWords will be sent by the Link Layer between each set of ALIGN primitive pairs. Note: If Send 4 Aligns is set, one should not set the Align Insertion Rate to be four or less. If Send 4 Aligns is not set, one should not set the Align Insertion Rate to be two or less. |
| EPNRT | 7 | rwNormal read/write | 0x0 | Enable Phy Not Ready Timer (EPNRT): If PhyReady is de-asserted for a length of time, as specified by Phy Ready Timer, then this bit, when asserted, enables the Link Layer to re-issue a PhyReset, thereby re-initiating OOB. |
| S4A | 6 | rwNormal read/write | 0x0 | Send 4 Aligns (S4A): When asserted, four ALIGN primitives are transmitted at the specified rate, instead of the normal two ALIGNS. |
| RXSE | 5 | rwNormal read/write | 0x1 | Rx Scramble Enable (RXSE): If this bit is asserted then de-scrambling of the Receive data is enabled as per the Serial ATA specification. |
| TXSE | 4 | rwNormal read/write | 0x1 | Tx Scramble Enable (TXSE): If this bit is asserted then scrambling of the Transmit data is enabled as per the Serial ATA specification. |
| TXPJ | 3 | rwNormal read/write | 0x0 | Tx Prim Junk (TXPJ): If this bit is de-asserted, then scrambled junk data is sent after a CONT primitive, as per the Serial ATA specification. If this bit is asserted, then the single character 32hDEADBEEF is sent continuously instead. This is to aid debug. |
| TXC | 2 | rwNormal read/write | 0x1 | Tx Cont (TXC): If this bit is asserted, then the transmission of CONT primitives is enabled. If de-asserted, then long sequences of repeated primitives can be sent by the Link Layer. |
| RXBC | 1 | rwNormal read/write | 0x0 | Rx Bad CRC (RXBC): When a rising edge is detected on this bit, it causes a bad CRC to be detected for the current frame. This bit has to be toggled from a 0 to a 1 to enable this feature. |
| TXBC | 0 | rwNormal read/write | 0x0 | Tx Bad CRC (TXBC): A bad CRC (inverted value of the correct CRC) value will be transmitted for one FIS only by the Link Layer when a rising edge is detected on this signal. This bit has to be toggled from a 0 to a 1 to enable this feature. |