ENC_CORE_CTRL (VCU_SLCR) Register Description
| Register Name | ENC_CORE_CTRL |
|---|---|
| Offset Address | 0x0000000030 |
| Absolute Address | 0x00A0040030 (VCU_SLCR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00001000 |
| Description | Reference clock control. |
ENC_CORE_CTRL (VCU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CLKACT | 12 | rwNormal read/write | 0x1 | Clock active signal. Switch to 0 to disable the clock |
| Reserved | 11:10 | razRead as zero | 0x0 | reserved |
| DIVISOR0 | 9:4 | rwNormal read/write | 0x0 | 6 bit divider |
| Reserved | 3:1 | razRead as zero | 0x0 | reserved |
| SRCSEL | 0 | rwNormal read/write | 0x0 | 0: clock input from PL to be used as encoder core clock. 1: clock derived from VCU PLL to be used as encoder core clock |