CTIOUTEN7 (CTI) Register Description
| Register Name | CTIOUTEN7 |
|---|---|
| Offset Address | 0x00000000BC |
| Absolute Address |
0x00FEBF80BC (CORESIGHT_R5_CTI_0) 0x00FEBF90BC (CORESIGHT_R5_CTI_1) 0x00FE9900BC (CORESIGHT_SOC_CTI_0) 0x00FE9A00BC (CORESIGHT_SOC_CTI_1) 0x00FE9B00BC (CORESIGHT_SOC_CTI_2) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | The CTI Channel to Trigger 7 Enable Registers define which channels can generate a ctitrigout[7] output. Within this register there is one bit for each of the four channels implemented. This register affects the mapping from application trigger to trigger outputs. |
CTIOUTEN7 (CTI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| TRIGOUTEN | 3:0 | rwNormal read/write | 0x0 | Changing the value of this bit from a 0 to a 1 enables a channel event for the corresponding channel to generate a ctitrigout[7] output. There is one bit of the field for each of the four channels.When a 1 is written to a bit in this register, the channel input (ctichin) from the CTM is routed to the ctitrigout output. For example, enabling bit 0 enables ctichin[0] to cause a trigger event on the ctitrigout[7] output. When a 0 is written to any of the bits in this register, the channel input (ctichin) from the CTM is not routed to the ctitrigout output.Reading this register returns the programmed value. |