INT_DIS_1 (GPIO) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

INT_DIS_1 (GPIO) Register Description

Register NameINT_DIS_1
Offset Address0x0000000254
Absolute Address 0x00FF0A0254 (GPIO)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionInterrupt Disable/Mask (GPIO Bank1, MIO)

This register operates in exactly the same manner as INT_DIS_0, except that it reflects bank1, which corresponds to MIO[51:26].

INT_DIS_1 (GPIO) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:26razRead as zero0x0Not used, read back as zero
INT_DISABLE_125:0woWrite-only0x0Interrupt disable
0: no change
1: set interrupt mask
Each bit configures the corresponding pin within the 26-bit bank