bank2_ctrl0 (IOU_SLCR) Register Description
| Register Name | bank2_ctrl0 |
|---|---|
| Offset Address | 0x0000000170 |
| Absolute Address | 0x00FF180170 (IOU_SLCR) |
| Width | 26 |
| Type | rwNormal read/write |
| Reset Value | 0x03FFFFFF |
| Description | MIO Bank 2, Drive 0 control. |
bank2_ctrl0 (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| drive0 | 25:0 | rwNormal read/write | 0x3FFFFFF | Together with the bank2_ctrl1 [drive1] bit field, controls the output drive strength of MIO pins [52:77]. Truthtable for [drive0], [drive1]: 00 = 2 mA 01 = 4 mA 10 = 8 mA 11 = 12 mA Bit [0] controls MIO pin 52. .. Bit [25] controls MIO pin 77. Bits [26] to [31] are reserved. |