PAXIC (SATA_AHCI_VENDOR) Register Description
| Register Name | PAXIC |
|---|---|
| Offset Address | 0x0000000020 |
| Absolute Address | 0x00FD0C00C0 (SATA_AHCI_VENDOR) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00410102 |
| Description | Port AXICfg |
Controls the configuration of the AXI Bus operation for either Port 0 or Port 1. The Port configured is controlled by the value programmed into the Port Config Register.
PAXIC (SATA_AHCI_VENDOR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:29 | roRead-only | 0x0 | Reserved |
| ENZP | 28 | rwNormal read/write | 0x0 | Enable non zero 4MB PRD Entries (ENZP) |
| AXIPT | 27 | rwNormal read/write | 0x0 | AXI Parity Type (AXIPT): 0: Even parity. 1: Odd parity. |
| AXIPE | 26 | rwNormal read/write | 0x0 | AXI Parity Enable (AXIPE): Parity Checking is enabled in the Link layer. The Parity is generated and checked on each byte within the 128 bit data busses on the Master interface |
| AAO | 25 | rwNormal read/write | 0x0 | Allow Address Overwrite (AAO): Command List Base Address [9:0] and FIS Base Address [7:0] to be overwritten |
| ECM | 24 | rwNormal read/write | 0x0 | Enable the Context management (ECM): system in the memory |
| OTL | 23:20 | rwNormal read/write | 0x4 | Outstanding Transfer Limit (OTL): This limits the maximum number of outstanding transfers supported: a) for the 264 DWords Transport Layer implementation this can be programmed between 1 and 16 b) for the 136 DWord Transport Layer implementation this can be programmed between 1 and 8 c) for the 72 DWord Transport Layer implementation this can be programmed between 1 and 4 0 = Transfers limited by the transport Layer FIFO space / fill level. |
| MARIDD | 19:16 | rwNormal read/write | 0x1 | Memory Address Read ID (MARIDD): for data transfers |
| MARID | 15:12 | rwNormal read/write | 0x0 | Memory Address read ID (MARID): for non data transfers |
| MAWIDD | 11:8 | rwNormal read/write | 0x1 | Memory Address write ID (MAWIDD): for data transfers |
| MAWID | 7:4 | rwNormal read/write | 0x0 | Memory Address write ID (MAWID): for non data transfers |
| Reserved | 3:2 | roRead-only | 0x0 | Reserved |
| ADBW | 1:0 | rwNormal read/write | 0x2 | AXI Data Bus Width (ADBW) 0: BW32. 1: BW64 (set to this value). 2: BW128. |