MIO_PIN_3 (IOU_SLCR) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

MIO_PIN_3 (IOU_SLCR) Register Description

Register NameMIO_PIN_3
Offset Address0x000000000C
Absolute Address 0x00FF18000C (IOU_SLCR)
Width32
TyperwNormal read/write
Reset Value0x00000000
DescriptionMIO Device Pin 3 Multiplexer Controls.

MIO_PIN_3 (IOU_SLCR) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
Reserved31:8rwNormal read/write0x0reserved
L3_SEL 7:5rwNormal read/write0x0Level 3 Mux Select:
0: GPIO [3] input/output bank 0.
1: CAN0 TX output.
2: I2C0 SDA input/output.
3: PJTAG TMS input.
4: SPI0 SS [0] input/output.
5: TTC2 waveform output.
6: UART0 TxD output.
7: TracePort DQ[1] output.
L2_SEL 4:3rwNormal read/write0x0Level 2 Mux Select:
0: Level 3 Mux output
1: reserved
2: Scan Test [3] input/output.
3: reserved
L1_SEL 2rwNormal read/write0x0Level 1 Mux Select:
0: Level 2 Mux output
1: reserved
L0_SEL 1rwNormal read/write0x0Level 0 Mux Select:
0: Level 1 Mux output
1: Quad SPI0 IO[3] input/output (lower).
Reserved 0rwNormal read/write0x0reserved