L3_TM_PLL_DIG_31 (SERDES) Register - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)
Document ID
UG1087
Release Date
2025-06-20
Revision
1.11

L3_TM_PLL_DIG_31 (SERDES) Register Description

Register NameL3_TM_PLL_DIG_31
Offset Address0x000000E07C
Absolute Address 0x00FD40E07C (SERDES)
Width32
TypemixedMixed types. See bit-field details.
Reset Value0x00000000
DescriptionRegister value is generated by Vivado PCW.

L3_TM_PLL_DIG_31 (SERDES) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
TM_PLL_DIG_31_31_8_rsvd31:8roRead-only0x0Value generated by PCW.
tm_clkdist_enable_master_clk_drive 7rwNormal read/write0x0Value generated by PCW.
tm_force_clkdist_enable_master_clk_drive 6rwNormal read/write0x0Value generated by PCW.
tm_clkdist_enable_lane_rst_drive 5rwNormal read/write0x0Value generated by PCW.
tm_force_clkdist_enable_lane_rst_drive 4rwNormal read/write0x0Value generated by PCW.
tm_clkdist_enable_lane_clk_drive 3rwNormal read/write0x0Value generated by PCW.
tm_force_clkdist_enable_lane_clk_drive 2rwNormal read/write0x0Value generated by PCW.
tm_clkdist_bias_rate_sel 1rwNormal read/write0x0Value generated by PCW.
tm_force_clkdist_bias_rate_sel 0rwNormal read/write0x0Value generated by PCW.