| Register Name | Offset Address | Width | Type | Reset Value | Description |
|---|
| reg_ctrl | 0x0000000000 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Miscellaneous control functions for SIOU |
| IR_STATUS | 0x0000000004 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| IR_MASK | 0x0000000008 | 32 | roRead-only | 0x00000001 | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| IR_ENABLE | 0x000000000C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
| IR_DISABLE | 0x0000000010 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| sata_misc_ctrl | 0x0000000100 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Misc Contorls for SATA.This register may only be modified during bootup (while SATA block is disabled) |
| crx_ctrl | 0x0000000410 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | crx_ctrl |
| dp_stc_clkctrl | 0x0000000430 | 32 | mixedMixed types. See bit-field details. | 0x00000001 | dp_stc_ref_clk control register |