SMMU_CIDR3 (SMMU500) Register Description
| Register Name | SMMU_CIDR3 |
|---|---|
| Offset Address | 0x0000000FFC |
| Absolute Address | 0x00FD800FFC (SMMU_GPV) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x000000B1 |
| Description | Component Identification register 3 |
SMMU_CIDR3 (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| PREAMBLE | 7:0 | roRead-only | 0xB1 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |