IOU_COHERENT_CTRL (IOU_SLCR) Register Description
| Register Name | IOU_COHERENT_CTRL |
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| Offset Address | 0x0000000400 |
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| Absolute Address |
0x00FF180400 (IOU_SLCR)
|
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| Width | 32 |
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| Type | rwNormal read/write |
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| Reset Value | 0x00000000 |
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| Description | AXI Coherency selection |
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Select the read/write transaction coherency and bufferability parameters for DMA AXI transactions of misc. IOP controllers. 0x0: Device non-bufferable. 0xF: Write-back-read and write-allocate. See Arm AMBA AXI and ACE Protocol Specification (IHI022E) for details. https://developer.arm.com/documentation/ihi0022/e/?lang=en
IOU_COHERENT_CTRL (IOU_SLCR) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| QSPI_AXI_COH | 31:28 | rwNormal read/write | 0x0 | Select Quad SPI DMA AxCache parameters. |
| NAND_AXI_COH | 27:24 | rwNormal read/write | 0x0 | Select NAND DMA AxCache parameters. |
| SD1_AXI_COH | 23:20 | rwNormal read/write | 0x0 | Select SDIO1 DMA AxCache parameters. |
| SD0_AXI_COH | 19:16 | rwNormal read/write | 0x0 | Select SDIO0 DMA AxCache parameters. |
| GEM3_AXI_COH | 15:12 | rwNormal read/write | 0x0 | Select GEM3 DMA AxCache parameters. |
| GEM2_AXI_COH | 11:8 | rwNormal read/write | 0x0 | Select GEM2 DMA AxCache parameters. |
| GEM1_AXI_COH | 7:4 | rwNormal read/write | 0x0 | Select GEM1 DMA AxCache parameters. |
| GEM0_AXI_COH | 3:0 | rwNormal read/write | 0x0 | Select GEM0 DMA AxCache parameters. |