Delay_REG (QSPI) Register Description
| Register Name | Delay_REG |
|---|---|
| Offset Address | 0x0000000018 |
| Absolute Address | 0x00FF0F0018 (QSPI) |
| Width | 32 |
| Type | rwNormal read/write |
| Reset Value | 0x00000000 |
| Description | Timing Control Delay |
This register is only used in master mode to introduce relative delays into the generation of the master output signals. All timings are defined in cycles of the SPI _REF_CLK/ext_clk, defined in this table as SPI master ref clock. Note: Change this value only when controller is not communicating with the memory device. Software Driver name: XQSPIPS_DR
Delay_REG (QSPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| d_nss | 31:24 | rwNormal read/write | 0x0 | Delay in SPI_REF_CLK or ext_clk cycles for the length that the master mode chip select outputs are de-asserted between words when cpha=0. |
| d_btwn | 23:16 | rwNormal read/write | 0x0 | Delay in SPI_REF_CLK or ext_clk cycles between one chip select being de-activated and the activation of another. Software Driver name: XQSPIPS_DR_BTWN |
| d_after | 15:8 | rwNormal read/write | 0x0 | Delay in SPI_REF_CLK or ext_clk cycles between last bit of current word and the first bit of the next word. Software Driver name: XQSPIPS_DR_AFTER |
| d_int | 7:0 | rwNormal read/write | 0x0 | Added delay in SPI_REF_CLK or ext_clk cycles between setting n_ss_out low and first bit transfer. Software Driver name: XQSPIPS_DR_INIT |