fpd_pipe_clk (USB3_REGS) Register Description
| Register Name | fpd_pipe_clk |
|---|---|
| Offset Address | 0x000000007C |
| Absolute Address |
0x00FF9D007C (USB3_0) 0x00FF9E007C (USB3_1) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | fpd_pipe_clk |
fpd_pipe_clk (USB3_REGS) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:1 | razRead as zero | 0x0 | reserved for future |
| option | 0 | rwNormal read/write | 0x0 | There is a requirement that USB2 cannot work without PIPE Rx/Tx clock toggling. So, we need to provide suspend_clk during FPD power down as well as SerDes not getting programmed. 1 meanss regular SeDes clock comes into USB PIPE interface. 0 means suspend clock comes |