CSUDMA Module - UG1087

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID

UG1087

Release Date

2024-03-13

Revision

1.10

CSUDMA Module Description

Module Name	CSUDMA Module
Modules of this Type	CSUDMA
Base Addresses	0x00FFC80000 (CSUDMA)
Description	CSU Module DMA Controller

CSUDMA Module Register Summary

Register Name	Offset Address	Width	Type	Reset Value	Description
CSUDMA_SRC_ADDR	0x0000000000	32	mixedMixed types. See bit-field details.	0x00000000	Source mem address (lsbs) for DMA memory->stream data transfer
CSUDMA_SRC_SIZE	0x0000000004	32	mixedMixed types. See bit-field details.	0x00000000	DMA transfer payload for DMA memory-> stream data transfer
CSUDMA_SRC_STS	0x0000000008	32	mixedMixed types. See bit-field details.	0x00000000	General SRC DMA Status
CSUDMA_SRC_CTRL	0x000000000C	32	mixedMixed types. See bit-field details.	0x003FFA00	General SRC DMA Control Register 1
CSUDMA_SRC_CRC	0x0000000010	32	rwNormal read/write	0x00000000	SRC DMA Pseudo CRC
CSUDMA_SRC_I_STS	0x0000000014	32	mixedMixed types. See bit-field details.	0x00000000	SRC DMA Interrupt Status Register
CSUDMA_SRC_I_EN	0x0000000018	32	mixedMixed types. See bit-field details.	0x00000000	SRC DMA Interrupt Enable
CSUDMA_SRC_I_DIS	0x000000001C	32	mixedMixed types. See bit-field details.	0x00000000	SRC DMA Interrupt Disable
CSUDMA_SRC_I_MASK	0x0000000020	32	mixedMixed types. See bit-field details.	0x0000007F	SRC DMA Interrupt Mask
CSUDMA_SRC_CTRL2	0x0000000024	32	mixedMixed types. See bit-field details.	0x0000FFF8	General SRC DMA Control Register 2
CSUDMA_SRC_ADDR_MSB	0x0000000028	32	mixedMixed types. See bit-field details.	0x00000000	Source mem address (msbs) for DMA memory->stream data transfer
CSUDMA_DST_ADDR	0x0000000800	32	mixedMixed types. See bit-field details.	0x00000000	Destination mem address (lsbs) for DMA stream->memory data transfer
CSUDMA_DST_SIZE	0x0000000804	32	mixedMixed types. See bit-field details.	0x00000000	DMA transfer payload for DMA stream-> memory data transfer
CSUDMA_DST_STS	0x0000000808	32	mixedMixed types. See bit-field details.	0x00000000	General DST DMA Status
CSUDMA_DST_CTRL	0x000000080C	32	rwNormal read/write	0x803FFA00	General DST DMA Control
CSUDMA_DST_I_STS	0x0000000814	32	mixedMixed types. See bit-field details.	0x00000000	DST DMA Interrupt Status Register
CSUDMA_DST_I_EN	0x0000000818	32	mixedMixed types. See bit-field details.	0x00000000	DST DMA Interrupt Enable
CSUDMA_DST_I_DIS	0x000000081C	32	mixedMixed types. See bit-field details.	0x00000000	DST DMA Interrupt Disable
CSUDMA_DST_I_MASK	0x0000000820	32	mixedMixed types. See bit-field details.	0x000000FE	DST DMA Interrupt Mask
CSUDMA_DST_CTRL2	0x0000000824	32	mixedMixed types. See bit-field details.	0x0000FFF8	General DST DMA Control Register 2
CSUDMA_DST_ADDR_MSB	0x0000000828	32	mixedMixed types. See bit-field details.	0x00000000	Destination mem address (msbs) for DMA stream->memory data transfer
CSUDMA_SAFETY_CHK	0x0000000FF8	32	rwNormal read/write	0x00000000	Safety endpoint connectivity check Register