PxIE (SATA_AHCI_PORTCNTRL) Register Description
| Register Name | PxIE |
|---|---|
| Offset Address | 0x0000000014 |
| Absolute Address |
0x00FD0C0114 (SATA_AHCI_PORT0_CNTRL) 0x00FD0C0194 (SATA_AHCI_PORT1_CNTRL) |
| Width | 32 |
| Type | mixedMixed types. See bit-field details. |
| Reset Value | 0x00000000 |
| Description | Port x Interrupt Enable (PxIE) |
Enables and disables the reporting of the corresponding interrupt to system software. When a bit is set to 1 and the corresponding interrupt condition is active, then an interrupt is generated. Interrupt sources that are disabled (set to 0) are still reflected in the status registers. This register is symmetrical with the PxIS register.
PxIE (SATA_AHCI_PORTCNTRL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| CPDE | 31 | rwNormal read/write | 0x0 | Cold Presence Detect Enable (CPDE): When set, GHC.IE is set, and PxS.CPDS is set, the HBA shall generate an interrupt. For systems that do not support cold presence detect, this bit shall be a read-only 0. |
| TFEE | 30 | rwNormal read/write | 0x0 | Task File Error Enable (TFEE): When set, GHC.IE is set, and PxS.TFES is set, the HBA shall generate an interrupt. |
| HBFE | 29 | rwNormal read/write | 0x0 | Host Bus Fatal Error Enable (HBFE): When set, GHC.IE is set, and PxIS.HBFS is set, the HBA shall generate an interrupt. |
| HBDE | 28 | rwNormal read/write | 0x0 | Host Bus Data Error Enable (HBDE): when set, GHC.IE is set, and PxIS.HBDS is set, the HBA shall generate an interrupt. |
| IFE | 27 | rwNormal read/write | 0x0 | Interface Fatal Error Enable (IFE): When set, GHC.IE is set, and PxIS.IFS is set, the HBA shall generate an interrupt. |
| INFE | 26 | rwNormal read/write | 0x0 | Interface Non-fatal Error Enable (INFE): When set, GHC.IE is set, and PxIS.INFS is set, the HBA shall generate an interrupt. |
| Reserved | 25 | roRead-only | 0x0 | Reserved |
| OFE | 24 | rwNormal read/write | 0x0 | Overflow Enable (OFE): When set, and GHC.IE and PxIS.OFS are set, the HBA shall generate an interupt. |
| IPME | 23 | rwNormal read/write | 0x0 | Incorrect Port Multiplier Enable (IPME): When set, and GHC.IE and PxIS.IPMS are set, the HBA shall generate an interupt. |
| PRCE | 22 | rwNormal read/write | 0x0 | PhyRdy Change Interrupt Enable (PRCE): When set to 1, and GHC.IE is set to 1, and PxIS.PRCS is set to 1, the HBA shall generate an interrupt. |
| Reserved | 21:8 | roRead-only | 0x0 | Reserved |
| DMPE | 7 | rwNormal read/write | 0x0 | Device Mechanical Presence Enable (DMPE): When set, and GHC.IE is set to 1, and PxIS.DMPS is set, the HBA shall generate an interrupt. For systems that do not support a mechanical presence switch, this bit shall be a read-only 0. |
| PCE | 6 | rwNormal read/write | 0x0 | Port Change Interrupt Enable (PCE): When set, GHC.IE is set, and PxIS.PCS is set, the HBA shall generate an interrupt. |
| DPE | 5 | rwNormal read/write | 0x0 | Descriptor Processed Interrupt Enable (DPE): When set, GHC.IE is set, and PxIS.DPS is set, the HBA shall generate an interrupt. |
| UFE | 4 | rwNormal read/write | 0x0 | Unknown FIS Interrupt Enable (UFE): When set, GHC.IE is set, and PxIS.UFS is set to 1, the HBA shall generate an interrupt. |
| SDBE | 3 | rwNormal read/write | 0x0 | Set Device Bits FIS Interrupt Enable (SDBE): When set, GHC.IE is set, and PxIS.SDBS is set, the HBA shall generate an interrupt. |
| DSE | 2 | rwNormal read/write | 0x0 | DMA Setup FIS Interrupt Enable (DSE): When set, GHC.IE is set, and PxIS.DSS is set, the HBA shall generate an interrupt. |
| PSE | 1 | rwNormal read/write | 0x0 | PIO Setup FIS Interrupt Enable (PSE): When set, GHC.IE is set, and PxIS.PSS is set, the HBA shall generate an interrupt. |
| DHRE | 0 | rwNormal read/write | 0x0 | Device to Host Register FIS Interrupt Enable (DHRE): When set, GHC.IE is set, and PxIS.DHRS is set, the HBA shall generate an interrupt. |