SMMU_CB9_ACTLR (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_CB9_ACTLR (SMMU500) Register Description

Register NameSMMU_CB9_ACTLR
Offset Address0x0000019004
Absolute Address 0x00FD819004 (SMMU_GPV)
Width32
TyperwNormal read/write
Reset Value0x00000003
DescriptionThe Auxillary Control register provides implementation specific configuration and control options.

SMMU_CB9_ACTLR (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
CPRE 1rwNormal read/write0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
CMTLB 0rwNormal read/write0x1Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details