PP0_MMU_STATUS (GPU) Register Description
| Register Name | PP0_MMU_STATUS |
|---|---|
| Offset Address | 0x0000004004 |
| Absolute Address | 0x00FD4B4004 (GPU) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000018 |
| Description | MMU Status Register |
PP0_MMU_STATUS (GPU) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| Reserved | 31:11 | roRead-only | 0x0 | Reserved, read as zero. |
| MMU_PAGE_FAULT_BUS_ID | 10:6 | roRead-only | 0x0 | Index of master responsible for last page fault. |
| MMU_PAGE_FAULT_IS_WRITE | 5 | roRead-only | 0x0 | The direction of access for last page fault. 0 = Read 1 = Write |
| MMU_REPLAY_BUFFER_EMPTY | 4 | roRead-only | 0x1 | The MMU replay buffer is empty. |
| MMU_IDLE | 3 | roRead-only | 0x1 | The MMU is idle when accesses are being translated and there are no unfinished translated accesses. The MMU_IDLE signal only reports idle when the MMU processor is idle and accesses are active on the external bus. |
| MMU_STALL_ACTIVE | 2 | roRead-only | 0x0 | MMU stall mode currently enabled. The mode is enabled by command. |
| MMU_PAGE_FAULT_ACTIVE | 1 | roRead-only | 0x0 | MMU page fault mode currently enabled. The mode is enabled by command. |
| MMU_PAGING_ENABLED | 0 | roRead-only | 0x0 | Paging is enabled. |