ZDMA Module Description
| Module Name | ZDMA Module |
|---|---|
| Modules of this Type | ADMA_CH0, ADMA_CH1, ADMA_CH2, ADMA_CH3, ADMA_CH4, ADMA_CH5, ADMA_CH6, ADMA_CH7, GDMA_CH0, GDMA_CH1, GDMA_CH2, GDMA_CH3, GDMA_CH4, GDMA_CH5, GDMA_CH6, GDMA_CH7 |
| Base Addresses |
0x00FFA80000 (ADMA_CH0) 0x00FFA90000 (ADMA_CH1) 0x00FFAA0000 (ADMA_CH2) 0x00FFAB0000 (ADMA_CH3) 0x00FFAC0000 (ADMA_CH4) 0x00FFAD0000 (ADMA_CH5) 0x00FFAE0000 (ADMA_CH6) 0x00FFAF0000 (ADMA_CH7) 0x00FD500000 (GDMA_CH0) 0x00FD510000 (GDMA_CH1) 0x00FD520000 (GDMA_CH2) 0x00FD530000 (GDMA_CH3) 0x00FD540000 (GDMA_CH4) 0x00FD550000 (GDMA_CH5) 0x00FD560000 (GDMA_CH6) 0x00FD570000 (GDMA_CH7) |
| Description | PS General Purpose DMA |
ZDMA Module Register Summary
| Register Name | Offset Address | Width | Type | Reset Value | Description |
|---|---|---|---|---|---|
| ZDMA_ERR_CTRL | 0x0000000000 | 32 | mixedMixed types. See bit-field details. | 0x00000001 | Enable/Disable a error response |
| ZDMA_CH_ISR | 0x0000000100 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Status Register for intrN. This is a sticky register that holds the value of the interrupt until cleared by a value of 1. |
| ZDMA_CH_IMR | 0x0000000104 | 32 | mixedMixed types. See bit-field details. | 0x00000FFF | Interrupt Mask Register for intrN. This is a read-only location and can be atomically altered by either the IDR or the IER. |
| ZDMA_CH_IEN | 0x0000000108 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Enable Register. A write of to this location will unmask the interrupt. (IMR: 0) |
| ZDMA_CH_IDS | 0x000000010C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Interrupt Disable Register. A write of one to this location will mask the interrupt. (IMR: 1) |
| ZDMA_CH_CTRL0 | 0x0000000110 | 32 | mixedMixed types. See bit-field details. | 0x00000080 | Channel Control Register 0 |
| ZDMA_CH_CTRL1 | 0x0000000114 | 32 | mixedMixed types. See bit-field details. | 0x000003FF | Channel Control Register 1 |
| ZDMA_CH_FCI | 0x0000000118 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Channel Flow Control Register |
| ZDMA_CH_STATUS | 0x000000011C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Channel Status Register |
| ZDMA_CH_DATA_ATTR | 0x0000000120 | 32 | mixedMixed types. See bit-field details. | 0x0483D20F | Channel DATA AXI parameter Register |
| ZDMA_CH_DSCR_ATTR | 0x0000000124 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Channel DSCR AXI parameter Register |
| ZDMA_CH_SRC_DSCR_WORD0 | 0x0000000128 | 32 | rwNormal read/write | 0x00000000 | SRC DSCR Word 0 |
| ZDMA_CH_SRC_DSCR_WORD1 | 0x000000012C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | SRC DSCR Word 1 |
| ZDMA_CH_SRC_DSCR_WORD2 | 0x0000000130 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | SRC DSCR Word 2 |
| ZDMA_CH_SRC_DSCR_WORD3 | 0x0000000134 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | SRC DSCR Word 3 |
| ZDMA_CH_DST_DSCR_WORD0 | 0x0000000138 | 32 | rwNormal read/write | 0x00000000 | DST DSCR Word 0 |
| ZDMA_CH_DST_DSCR_WORD1 | 0x000000013C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DST DSCR Word 1 |
| ZDMA_CH_DST_DSCR_WORD2 | 0x0000000140 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DST DSCR Word 2 |
| ZDMA_CH_DST_DSCR_WORD3 | 0x0000000144 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DST DSCR Word 3 |
| ZDMA_CH_WR_ONLY_WORD0 | 0x0000000148 | 32 | rwNormal read/write | 0x00000000 | Write Only Data Word 0 |
| ZDMA_CH_WR_ONLY_WORD1 | 0x000000014C | 32 | rwNormal read/write | 0x00000000 | Write Only Data Word 1 |
| ZDMA_CH_WR_ONLY_WORD2 | 0x0000000150 | 32 | rwNormal read/write | 0x00000000 | Write Only Data Word 2 |
| ZDMA_CH_WR_ONLY_WORD3 | 0x0000000154 | 32 | rwNormal read/write | 0x00000000 | Write Only Data Word 3 |
| ZDMA_CH_SRC_START_LSB | 0x0000000158 | 32 | rwNormal read/write | 0x00000000 | SRC DSCR Start Address LSB Register |
| ZDMA_CH_SRC_START_MSB | 0x000000015C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | SRC DSCR Start Address MSB Register |
| ZDMA_CH_DST_START_LSB | 0x0000000160 | 32 | rwNormal read/write | 0x00000000 | DST DSCR Start Address LSB Register |
| ZDMA_CH_DST_START_MSB | 0x0000000164 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DST DSCR Start Address MSB Register |
| ZDMA_CH_TOTAL_BYTE | 0x0000000188 | 32 | wtcReadable, write a 1 to clear | 0x00000000 | Total Bytes Transferred Register |
| ZDMA_CH_RATE_CTRL | 0x000000018C | 32 | mixedMixed types. See bit-field details. | 0x00000000 | Rate Control Count Register |
| ZDMA_CH_IRQ_SRC_ACCT | 0x0000000190 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | SRC Interrupt Account Count Register |
| ZDMA_CH_IRQ_DST_ACCT | 0x0000000194 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | DST Interrupt Account Count Register |
| ZDMA_CH_CTRL2 | 0x0000000200 | 32 | mixedMixed types. See bit-field details. | 0x00000000 | zDMA Control Register 2 |