EXTENDED_IDCODE (EFUSE) Register Description
| Register Name | EXTENDED_IDCODE |
|---|---|
| Offset Address | 0x0000001018 |
| Absolute Address | 0x00FFCC1018 (EFUSE) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000000 |
| Description | Available Functionality |
The device family can be determined using the VCU_DIS & GPU_DIS bits: 00: EV (includes VCU and GPU) 01: Invalid 10: EG (includes GPU) 11: CG (no VCU or GPU; 2-core)
EXTENDED_IDCODE (EFUSE) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| VCU_DIS | 8 | roRead-only | 0x0 | 0: VCU is present 1: VCU is not present Note:this bit is only valid if the PL is powered-up and the PROG_B signal is released. |
| GPU_DIS | 5 | roRead-only | 0x0 | 0: GPU is present 1: GPU is not present |
| APU3_DIS | 3 | roRead-only | 0x0 | Indicates that APU core 3 is disabled if set |
| APU2_DIS | 2 | roRead-only | 0x0 | Indicates that APU core 2 is disabled if set |
| APU1_DIS | 1 | roRead-only | 0x0 | Indicates that APU core 1 is disabled if set |
| APU0_DIS | 0 | roRead-only | 0x0 | Indicates that APU core 0 is disabled if set |