PL_2_IMR (IPI) Register Description
| Register Name | PL_2_IMR |
|---|
| Offset Address | 0x0000060014 |
|---|
| Absolute Address |
0x00FF360014 (IPI)
|
|---|
| Width | 32 |
|---|
| Type | roRead-only |
|---|
| Reset Value | 0x0F0F0301 |
|---|
| Description | Ch 9 Interrupt Mask (receiver). |
|---|
Read-only. 0: enabled. 1: masked (disabled). Note: If the ISR bit = 1 (asserted interrupt) and the IMR bit = 0 (not masked), then the IRQ to the interrupt controller is asserted.
PL_2_IMR (IPI) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:28 | roRead-only | 0x0 | reserved |
| PL_3 | 27 | roRead-only | 0x1 | Ch 10. Default to PL IPI3. |
| PL_2 | 26 | roRead-only | 0x1 | Ch 9. Default to PL IPI2. |
| PL_1 | 25 | roRead-only | 0x1 | Ch 8. Default to PL IPI1. |
| PL_0 | 24 | roRead-only | 0x1 | Ch 7. Default to PL IPI0. |
| Reserved | 23:20 | roRead-only | 0x0 | reserved |
| PMU_3 | 19 | roRead-only | 0x1 | Ch 6: PMU IPI3. |
| PMU_2 | 18 | roRead-only | 0x1 | Ch 5: PMU IPI2. |
| PMU_1 | 17 | roRead-only | 0x1 | Ch 4: PMU IPI1. |
| PMU_0 | 16 | roRead-only | 0x1 | Ch 3: PMU IPI0. |
| Reserved | 15:10 | roRead-only | 0x0 | reserved |
| RPU_1 | 9 | roRead-only | 0x1 | Ch 2. Default to RPU1. |
| RPU_0 | 8 | roRead-only | 0x1 | Ch 1. Default to RPU0. |
| Reserved | 7:1 | roRead-only | 0x0 | reserved |
| APU | 0 | roRead-only | 0x1 | Ch 0. Default to APU MPCore. |