SMMU_PIDR4 (SMMU500) Register Description
| Register Name | SMMU_PIDR4 |
|---|---|
| Offset Address | 0x0000000FD0 |
| Absolute Address | 0x00FD800FD0 (SMMU_GPV) |
| Width | 32 |
| Type | roRead-only |
| Reset Value | 0x00000004 |
| Description | Peripheral Identificaation register 4 |
SMMU_PIDR4 (SMMU500) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|---|---|---|---|
| FourKB_Count | 7:4 | roRead-only | 0x0 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |
| JEP106_Continuation_code | 3:0 | roRead-only | 0x4 | Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details |