OCM_PWR_CNTRL (PMU_LOCAL) Register Description
| Register Name | OCM_PWR_CNTRL |
|---|
| Offset Address | 0x00000000C0 |
|---|
| Absolute Address |
0x00FFD600C0 (PMU_LOCAL)
|
|---|
| Width | 32 |
|---|
| Type | mixedMixed types. See bit-field details. |
|---|
| Reset Value | 0x01010101 |
|---|
| Description | OCM Memory Power Control. Reset only by POR. |
|---|
Controls the power switch gate: 0: power off. 1: power on. All fields can only be read or written by the PMU processor. This register maintains its contents during a System Reset.
OCM_PWR_CNTRL (PMU_LOCAL) Register Bit-Field Summary
| Field Name | Bits | Type | Reset Value | Description |
|---|
| Reserved | 31:25 | roRead-only | 0x0 | reserved |
| Bank3 | 24 | rwNormal read/write | 0x1 | OCM Bank 3 |
| Reserved | 23:17 | roRead-only | 0x0 | reserved |
| Bank2 | 16 | rwNormal read/write | 0x1 | OCM Bank 2 |
| Reserved | 15:9 | roRead-only | 0x0 | reserved |
| Bank1 | 8 | rwNormal read/write | 0x1 | OCM Bank 1 |
| Reserved | 7:1 | roRead-only | 0x0 | reserved |
| Bank0 | 0 | rwNormal read/write | 0x1 | OCM Bank 0 |