enable_component_id_1 (PL390) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

enable_component_id_1 (PL390) Register Description

Register Nameenable_component_id_1
Offset Address0x0000000FF4
Absolute Address 0x00F9000FF4 (RCPU_GIC)
Width 8
TyperoRead-only
Reset Value0x000000F0
DescriptionThe component_id_[3:0] Registers are four eight-bit wide registers,
that can conceptually be treated as a single register that holds a
32-bit PrimeCell ID value.

enable_component_id_1 (PL390) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
component_id_1 7:0roRead-only0xF0These bits read back as 0xF0.