SMMU_CB3_PMCNTENSET (SMMU500) Register

Zynq UltraScale+ Devices Register Reference (UG1087)

Document ID
UG1087
Release Date
2024-03-13
Revision
1.10

SMMU_CB3_PMCNTENSET (SMMU500) Register Description

Register NameSMMU_CB3_PMCNTENSET
Offset Address0x0000013F48
Absolute Address 0x00FD813F48 (SMMU_GPV)
Width32
TypewoWrite-only
Reset Value0x00000000
DescriptionProvides the equivalent of the PMINTENSETx in the register map of a translation context bank. Enables the generation of interrupt requests on overflows from each implemented event counter

SMMU_CB3_PMCNTENSET (SMMU500) Register Bit-Field Summary

Field NameBitsTypeReset ValueDescription
P3 3woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P2 2woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P1 1woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details
P0 0woWrite-only0Refer to Arm SMMU v2 Architecture Spec (Arm IHI0062B) for more details