Field Name | Bits | Type | Reset Value | Description |
Reserved | 31 | rwNormal read/write | 0x0 | reserved |
Reserved | 30 | rwNormal read/write | 0x0 | reserved |
Reserved | 29 | rwNormal read/write | 0x0 | reserved |
afifs2 | 28 | rwNormal read/write | 0x0 | AIB_AXI for AFIFS2 |
lpd_ddr | 27 | rwNormal read/write | 0x0 | AIB_AXI for LPD to DDR path |
ocms | 26 | rwNormal read/write | 0x0 | AIB_AXI for OCM |
Reserved | 25 | rwNormal read/write | 0x0 | reserved |
fpd_main | 24 | rwNormal read/write | 0x0 | AIB_AXI between LPD and FPD main |
usb1s | 23 | rwNormal read/write | 0x0 | AIB_AXI for USB1 Slave |
usb0s | 22 | rwNormal read/write | 0x0 | AIB_AXI for USB0 Slave |
Reserved | 21 | rwNormal read/write | 0x0 | reserved |
Reserved | 20 | rwNormal read/write | 0x0 | reserved |
rpus1 | 19 | rwNormal read/write | 0x0 | AIB_AXI for RPU_1 Slave |
rpus0 | 18 | rwNormal read/write | 0x0 | AIB_AXI for RPU_0 Slave |
rpum1 | 17 | rwNormal read/write | 0x0 | AIB_AXI for RPU_1 Master |
rpum0 | 16 | rwNormal read/write | 0x0 | AIB_AXI for RPU_0 Master |
Reserved | 15 | rwNormal read/write | 0x0 | reserved |
Reserved | 14 | rwNormal read/write | 0x0 | reserved |
Reserved | 13 | rwNormal read/write | 0x0 | reserved |
Reserved | 12 | rwNormal read/write | 0x0 | reserved |
Reserved | 11 | rwNormal read/write | 0x0 | reserved |
Reserved | 10 | rwNormal read/write | 0x0 | reserved |
Reserved | 9 | rwNormal read/write | 0x0 | reserved |
Reserved | 8 | rwNormal read/write | 0x0 | reserved |
Reserved | 7 | rwNormal read/write | 0x0 | reserved |
Reserved | 6 | rwNormal read/write | 0x0 | reserved |
Reserved | 5 | rwNormal read/write | 0x0 | reserved |
Reserved | 4 | rwNormal read/write | 0x0 | reserved |
fpd_ocm | 3 | rwNormal read/write | 0x0 | AIB_AXI for FPD to LPD OCM path |
fpd_lpdibs | 2 | rwNormal read/write | 0x0 | AIB_AXI for FPD to LPD Interconnect path |
afifs1 | 1 | rwNormal read/write | 0x0 | AIB_AXI for AFI_FS1 Slave |
afifs0 | 0 | rwNormal read/write | 0x0 | AIB_AXI for AFI_FS0 Slave |